Ching Thiam Chung
3Patents
2h-index
6Co-inventors
30Inventor score
Filing activity: Apr 30, 2002 → Apr 6, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6713335B2 | Method of self-aligning a damascene gate structure to isolation regions | Electricity | 7 | Expired |
| US6743694B2 | Method of wafer marking for multi-layer metal processes | Electricity | 6 | Expired |
| US7376920B2 | Method to monitor critical dimension of IC interconnect | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.