Fei Wei
7Patents
1h-index
21Co-inventors
43Inventor score
Filing activity: Mar 26, 2019 → Oct 16, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11204765B1 | Deferred GPR allocation for texture/load instruction block | Physics | 3 | Active |
| US12045928B2 | Ray tracing processor | Physics | 0 | Active |
| US12229215B2 | Performing matrix multiplication in a streaming processor | Physics | 0 | Active |
| US12229864B2 | Runtime mechanism to optimize shader execution flow | Physics | 0 | Active |
| US11132760B2 | Graphics instruction operands alias | Physics | 0 | Active |
| US11094103B2 | General purpose register and wave slot allocation in graphics processing | Physics | 0 | Active |
| US11829439B2 | Methods and apparatus to perform matrix multiplication in a streaming processor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.