John E. Spracklen
12Patents
11h-index
10Co-inventors
65Inventor score
Filing activity: May 1, 1980 → Aug 28, 1998
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5487156A | Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched | Physics | 206 | Expired |
| US5625837A | Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code | Physics | 128 | Expired |
| US5561776A | Processor architecture supporting multiple speculative branching | Physics | 123 | Expired |
| US4332027A | Local area contention network data communication system | Electricity | 116 | Expired |
| US5627983A | Processor architecture providing out-of-order execution | Physics | 89 | Expired |
| US5592636A | Processor architecture supporting multiple speculative branches and trap handling | Physics | 81 | Expired |
| US5832293A | Processor architecture providing speculative, out of order execution of instructions and trap handling | Physics | 78 | Expired |
| US5708841A | Processor architecture providing speculative, out of order execution of instructions | Physics | 77 | Expired |
| US5797025A | Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching | Physics | 74 | Expired |
| US4337465A | Line driver circuit for a local area contention network | Electricity | 45 | Expired |
| US4413258A | Interconnection for local area contention networks | Electricity | 17 | Expired |
| US5987588A | Processor architecture providing for speculative execution of instructions with multiple predictive branching and handling of trap conditions | Physics | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.