Joseph Sheredy
10Patents
4h-index
8Co-inventors
49Inventor score
Filing activity: Jan 9, 2002 → Feb 14, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7948798B1 | Mixed multi-level cell and single level cell storage device | Physics | 38 | Active |
| US7308530B1 | Architecture for a data storage device | Physics | 16 | Expired |
| US10209902B1 | Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data | Physics | 10 | Active |
| US9244834B2 | Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data | Physics | 6 | Active |
| US9898212B1 | Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data | Physics | 4 | Active |
| US7062423B1 | Method and apparatus for testing a system on a chip (SOC) integrated circuit comprising a hard disk controller and read channel | Physics | 3 | Expired |
| US8135913B1 | Mixed multi-level cell and single level cell storage device | Physics | 3 | Active |
| US8086935B1 | Soft error correction for a data storage mechanism | Physics | 2 | Active |
| US8495320B1 | Method and apparatus for storing data in a flash memory including single level memory cells and multi level memory cells | Physics | 2 | Active |
| US7870342B2 | Line cache controller with lookahead | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.