TaeJin Pyon
6Patents
1h-index
6Co-inventors
36Inventor score
Filing activity: Jan 23, 2015 → Sep 13, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11119910B2 | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments | Emerging Cross-Sectional Technologies | 1 | Active |
| US10546625B2 | Method of optimizing write voltage based on error buffer occupancy | Physics | 1 | Active |
| US9281028B1 | Method and circuit for glitch reduction in memory read latch circuit | Physics | 1 | Active |
| US11580014B2 | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments | Emerging Cross-Sectional Technologies | 0 | Active |
| US11119936B2 | Error cache system with coarse and fine segments for power optimization | Emerging Cross-Sectional Technologies | 0 | Active |
| US11586553B2 | Error cache system with coarse and fine segments for power optimization | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.