Input-output device management using dynamic clock frequency
US10001830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2015 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Sep 6, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an example, a method includes determining, at a host device, a power state of a digital input/output device, and transmitting a clock signal having a first frequency from the host device to the input/output device responsive to a determination that the input/output device is in a lower power state. The method also includes determining, at the host device, that the input/output device has transitioned into a higher power state, and transmitting a clock signal having a second frequency from the host device to the input/output device responsive to a determination that the input/output device has transitioned into the higher power state. The first frequency is lower than the second frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.