Packed data alignment plus compute instructions, processors, methods, and systems
US10001995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2015 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Feb 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.