Memory devices and modules
US10002043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2015 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Apr 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.