Method and apparatus for managing mismatches within a multi-threaded lockstep processing system
US10002057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2016 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Nov 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.