High-precision analog-to-digital converter and DNL-based performance improvement method
US10003352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2015 |
| Grant date | Jun 19, 2018 |
| Priority date | — |
| Expiry date | Jun 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.