Board, integrated circuit testing arrangement, and method for operating an integrated circuit
US10006942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2013 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Mar 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10378
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A board may include a first set of board contact pads arranged on a first side of the board, the pads configured to connect to circuit pads of a circuit under test, the positions of the pads matching to the positions of the circuit pads; a fan-out region on the first side of the board including fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad connecting to at least one pad of the first set of board pads; and a second set of board contact pads on a second side of the board, the second set of board pads configured to connect to test board pads of a test board; positions of the pads matching to the positions of the test board pads; a pad connecting to a pad of the first set of board pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.