Time-to-digital converter with phase-scaled course-fine resolution
US10007235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Sep 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time-to-digital converter (TDC) measures a time interval ΔTTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=ΔTTot−mTNOR to obtain a value for the time interval ΔTTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.