Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power
US10007321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Feb 7, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.