Multi-source address translation service (ATS) with a single ATS resource
US10007618B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Mar 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.