PLL system with master and slave devices
US10007639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Sep 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.