V-gate layout and gate drive configuration
US10008139B2 · kind B2 · utility
0Cited by
5References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 14, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device may include a plurality of pixels, a plurality of source lines that may provide a plurality of data line signals to the plurality of pixels, a plurality of gate lines that may provide a plurality of gate signals to a plurality of switches associated with the plurality of pixels, and a plurality of voltage gate lines disposed parallel to the plurality of source lines and coupled to the plurality of gate lines at a plurality of cross point nodes. The plurality of cross point nodes are positioned in a pseudo random order across the display device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.