Sense amplifier in low power and high performance SRAM
US10008261B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Sep 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.