Embedded SiGe epitaxy test pad
US10008420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.