Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
US10008425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2016 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Nov 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods of manufacturing such circuits are disclosed herein that feature metal line-via matrix insertion after place and route processes are performed and/or completed for the integrated circuit's layout. The metal line-via matrix consists of one or more additional metal lines and one or more additional vias that are inserted into the integrated circuit's layout at a specific point to lower the current and current density through a first conductive path that has been determined to suffer from electromigration, IR-voltage drop, and/or jitter. Specifically, the metal line-via matrix provides one or more auxiliary conductive paths to divert and carry a portion of the current that would otherwise flow through the first conductive path. This mitigates electromigration issues and IR-voltage drop along the first conductive path. It may also help alleviate problems due to jitter along the path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.