Display device having reduced parasitic capacitance and cross-talk and method of manufacturing the same
US10008517B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Oct 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/423
Abstract
A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a plurality of pixels, wherein each pixel includes a scan line extending in a first direction. Each pixel also includes a data line extending in a second direction crossing the first direction and a driving thin-film transistor (TFT) formed adjacent to the data line and including a gate electrode, a source electrode, and a drain electrode. The pixel also includes an interlayer insulating layer formed between the data line and the driving TFT, and a first through hole is formed in the interlayer insulating layer to be adjacent to the data line and the gate electrode. Each pixel also includes a driving voltage line formed adjacent to the data line and including a first portion formed in the first through hole and formed on the interlayer insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.