Circuit arrangement for the thermal protection of a power semiconductor
US10008847B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention concerns a circuit arrangement for thermal protection of a power semiconductor, wherein there is provided a two-stage thermal protection in the control circuit and in the load circuit of the power semiconductor. A first stage (10) with temperature-dependent resistance device serves for reducing or switching off the control voltage of the power semiconductor (30) when a first threshold temperature is reached at the temperature-dependent resistance device. In addition, provided in the load circuit of the power semiconductor (30) is a second stage (20) with a cutout element thermally coupled to the power semiconductor (30) for interrupting a load current of the power semiconductor when a second threshold temperature is reached at the cutout element. In that case the first stage forms an active temperature protection for the power semiconductor (30) to avoid damage and the second stage forms a temperature protection in the case of a malfunction of the power semiconductor (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.