Repeat execution of root cause analysis logic through run-time discovered topology pattern maps
US10009216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2015 |
| Grant date | Jun 26, 2018 |
| Priority date | — |
| Expiry date | Jul 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and computer program products for repeat execution of RCA logic through run-time discovered topology pattern maps are provided herein. A computer-implemented method includes determining one or more topology paths of configuration items from a collection of multiple views of a target system; identifying one or more patterns from the one or more topology paths of configuration items; comparing the one or more identified patterns against a collection of data comprising mappings between (i) multiple root cause analysis logical expressions and (ii) multiple system architecture patterns, thereby identifying one or more of the multiple root cause analysis logical expressions to be executed on the one or more topology paths of configuration items; and generating a user-accessible link via a uniform resource locator for direct invocation of the one or more identified multiple root cause analysis logical expressions executed on the one or more topology paths of configuration items.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.