System on chip and secure debugging method
US10012693B2 · kind B2 · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Sep 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31719
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system on chip (SoC) is provided. The system on chip includes a multiprocessor that includes multiple processors, a debugging controller that includes a debug port and retention logic configured to store an authentication result of a secure joint test action group system, and a power management unit configured to manage power supplied to the multiprocessor and the debugging controller. The power management unit changes the debug port and the retention logic into an alive power domain in response to a debugging request signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.