Hardware-based run-time mitigation of conditional branches
US10013255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Sep 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45516
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.