Semiconductor memory device having rank interleaving operation in memory module
US10013341B2 · kind B2 · utility
5Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Dec 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first memory area in the semiconductor memory device, and a second memory area in the semiconductor memory device. The second memory area is accessed independently of the first memory area based on a usage selecting signal. The first and second memory areas share command and address lines, and perform a rank interleaving operation based on the usage selecting signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.