Non-blocking parallel memory mechanisms
US10013347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2015 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Jan 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transaction descriptor associated with a vertical chain of row versions is received. The vertical chain of row versions is traversed. The vertical chain is part of a grid structure formed by a number of vertical chains intersected with a number of horizontal chains. A link to a current row version is terminated. A link from the current row version to an older row version in a horizontal chain is locally stored and terminated. The older row version is set as ready for garbage collection. The current row version is set as ready for garbage collection. A link from the current row version to a next row version in the horizontal chain is locally stored and terminated. The next row version is appointed as current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.