Split memory bank
US10014055B2 · kind B2 · utility
2Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2014 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Jul 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.