Methods of forming patterns with multiple layers for semiconductor devices
US10014181B2 · kind B2 · utility
1Cited by
1References
19Claims
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Key dates
| Filing date | Jul 20, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Jul 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming patterns for semiconductor devices are provided. A method may include preparing a substrate including an etch target layer on a surface of the substrate; forming a mask pattern that includes a lower masking layer having a first density and an upper masking layer having a second density that is less than the first density, on the etch target layer; forming spacers that cover sidewalls of the lower masking layer and the upper masking layer; removing the mask pattern; and etching the etch target layer by using the spacers as an etching mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.