Method for manufacturing semiconductor device using high speed epitaxial lift-off and template for III-V direct growth and semiconductor device manufactured using the same
US10014216B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Sep 15, 2015 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Oct 2, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for manufacturing a semiconductor device, which includes providing a template having a first substrate and a patterned first III-V group compound layer located on the first substrate, forming a sacrificial layer on the patterned first III-V group compound layer by epitaxial growth, forming a second III-V group compound layer on the sacrificial layer by epitaxial growth, bonding a second substrate made of silicon onto the second III-V group compound layer, and separating the second III-V group compound layer and the second substrate from the template by removing the sacrificial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.