Methods for fabricating metal gate structures
US10014225B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2017 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One aspect of the present disclosure is a method of fabricating metal gate by forming a silicon-nitride layer (SiN) over a dummy gate at a second metal gate type transistor region (e.g. NMOS) avoid dummy gate loss during a CMP process for a PMOS gate. The method can comprise after performing a patterning process to remove hard masks at PMOS and NMOS regions, forming a SiN layer over the NMOS region; performing a patterning process to open the PMOS region and filling gate materials in the PMOS region; performing a CMP to polish a top surface of PMOS such that the polishing stops at SiN. In this way, dummy gate loss can be reduced during the first aluminum CMP step and thus can reduce initial height of dummy gate as compared to the convention method, and improve the filling process of the dummy gate as compared to the conventional method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.