Patent · US Active

Semiconductor device manufacturing method including implementing elements of memory unit and logic unit

US10014307B2 · kind B2 · utility

1Cited by
5References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 7, 2015
Grant dateJul 3, 2018
Priority date
Expiry dateDec 7, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/035

Abstract

A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.