Electronic chip manufacturing method

US10014308B2 · kind B2 · utility

Assignee

• STMicroelectronics (Crolles 2) SAS · FR

Inventors

• Stephane Zoll · Mazaretiers, FR
• Philippe Garnier · Epagny, FR

Key dates

• Filing date: Aug 4, 2016
• Grant date: Jul 3, 2018
• Expiry date: Aug 4, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/693

Abstract

Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.