Array substrate with thin film transistor and method of manufacturing the same
US10014329B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 11, 2014 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Oct 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
Abstract
An array substrate and manufacturing method thereof and display device are provided. The method of manufacturing the array substrate includes forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate; forming a pattern including a data line, a source electrode, a drain electrode and an active layer; forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer; forming a pattern including a first transparent electrode over the insulating interlayer; forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including a second transparent electrode over the passivation layer. The method can efficiently prevent the ITO process polluting the TFT channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.