DC bias circuit and the radio frequency receiver circuit using the same
US10014830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2015 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.