Apparatus and method for inhibiting roundoff error in a floating point argument reduction operation
US10019232B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Jul 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for inhibiting roundoff error in a floating point argument reduction operation. The apparatus has reciprocal estimation circuitry that is responsive to a first floating point value to determine a second floating point value that is an estimated reciprocal of the first floating point value. During this determination, the second floating point value has both its magnitude and its error bound constrained in dependence on a specified value N. Argument reduction circuitry then performs an argument reduction operation using the first and second floating point values as inputs, in order to generate a third floating point value. The use of the specified value N to constrain both the magnitude and the error bound of the second floating point value causes roundoff error to be inhibited in the third floating point value that is generated by the argument reduction operation. This enables such an argument reduction operation to be used as part of a more complex computation, such as a logarithm computation, with the inhibiting of roundoff error in the argument reduction result allowing the overall result to exhibit small relative error across the whole repres…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.