Security control system for protection of multi-core processors
US10019576B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Jan 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/566
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A security control system is provided that works as an extra layer of defense as a way to prevent an “attack” that is initiated by modifying either the “jump” or the “return” addresses or both. The principal behind the security control system is to “monitor” the addresses to which the processors would jump, interrupt or return, and identify when these addresses are modified in a manner that does not comply with the normal execution of the processor. In order to do that the security control system uses existing structures in multi-core processors and even anticipates the creation of additional structures to expedite and improve such control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.