Pixel compensation circuits, scanning driving circuits and flat display devices
US10019943B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Sep 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to pixel compensation circuit, pixel compensation method and flat display device. Control ends of first to third, fourth, and fifth controllable transistors connect to first to third, third, and fourth scanning lines, first end of first controllable transistor connects to data line, control end of driving transistor connects to second ends of first controllable transistor, and second controllable transistors through storage capacitor, and first end of third controllable transistor; first end of second controllable transistor connects to first voltage end, second end of driving transistor connects to second end of second controllable transistor and anode of OLED; cathode of OLED is grounded; first end of driving transistor connects to second ends of third and fifth controllable transistors and first end of fourth controllable transistor, second end of fourth controllable transistor connects to reference voltage end; first end of fifth controllable transistor connects to second voltage end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.