Integrated circuits and methods for dynamic allocation of one-time programmable memory
US10020067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a one-time programmable (OTP) memory having a plurality of pages and address translation circuitry. A first line of each page is configured to store error policy bits. When a first bit of the first line has a first value, the page is configured to store data with error correction code (ECC) bits, and when the first bit has a second value, at least a portion of the page is configured to store data with redundancy. The address translation circuitry is configured to, in response to receiving an access address, use the first line of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.