Multiplexer distortion cancellation
US10020068B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Sep 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Distortion in a combined sample and hold circuit and multiplexer can be reduced by dividing the sample and hold circuit and the multiplexer up into main and compensation signal channels, and considering the total error signal that arises during an acquire phase across both the switches of the multiplexer and the input switches of the sample and hold stage as a single error signal that has to be compensated. This compensation is then achieved by causing the same error voltages to be induced in both the main and compensation channels of the whole MUX and sample and hold circuit, such that errors can be made to cancel, thus improving the performance of the stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.