Semiconductor memory device provided with DRAM cell including two transistors and common capacitor

US10020311B1 · kind B1 · utility

Assignee

• AP MEMORY TECHNOLOGY CORPORATION · TW

Inventors

• Owen Li · Zhubei City, TW
• Wenliang Chen · Tianjin, CN

Key dates

• Filing date: Aug 2, 2017
• Grant date: Jul 10, 2018
• Expiry date: Aug 2, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A semiconductor memory device is provided such as a random-access memory (DRAM) including a plurality of DRAM memory cells. Each of the DRAM cells includes an N-type transistor, a P-type transistor, and a common capacitor. The components are disposed in the same direction as the bit-line, with the common capacitor occupying the center region between the N- and P-type transistors. The common capacitor is a metal insulator metal (MIM) capacitor configured by connecting three capacitor elements in parallel. The three capacitors include a first capacitor element formed on a first source/drain region of the N-type transistor, a second capacitor element formed on a first source/drain region of the P-type transistor, and a third element over the field isolation region between the transistors. A bottom electrode of each of these capacitor elements connects the first source/drain region of the N-type transistor to a first source/drain region of the P-type transistor.