Patent · US Active

FPGA RAM blocks optimized for use as register files

US10020811B2 · kind B2 · utility

0Cited by

17References

16Claims

0Family size

Assignee

Microsemi SoC Corp. · US

Inventors

Joel Landry · Colorado Springs, US
Jonathan W. Greene · Palo Alto, US
William C. Plants · Santa Clara, US
Wenyi Feng · 流花街道, CN

Key dates

Filing date	Sep 25, 2017
Grant date	Jul 10, 2018
Priority date	—
Expiry date	Sep 25, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/1776
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.