Hybrid successive approximation register analog to digital converter
US10020816B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2017 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Aug 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and circuitries for converting an analog voltage to a digital signal are provided. In one example a method to convert an analog voltage into a binary sequence that represents the voltage includes two modes. In the first mode, in each cycle, values for a next two or more of consecutive most significant bits (MSBs) in the sequence are determined using M comparators, wherein M is equal to or greater than 3. In a second mode, in each cycle, M redundant comparison results are determined using the M comparators. A value for the LSB is determined based on the M redundant values. At an end of conversion, the sequence of N bit values is generated based on the MSBs and the LSB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.