Lithography process for the encapsulation of patterned thin film coatings
US10025189B2 · kind B2 · utility
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Key dates
| Filing date | Jul 15, 2016 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Jul 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0272
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A single lithography process for multi-layer metal/dielectric coatings using a series of developing, baking, and lifting steps to coat two or more thin films without re-patterning that results in the encapsulation and profile optimization of multi-spectral patterned thin film coatings is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.