Patent · US Active

Data transfer between asynchronous clock domains

US10025343B2 · kind B2 · utility

2Cited by

11References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Michael C. Rifani · Beaverton, US
Alan B. Kyker · Davis, US
Alan S. Geist · Portland, US
David M. Lee · Portland, US

Key dates

Filing date	Dec 28, 2011
Grant date	Jul 17, 2018
Priority date	—
Expiry date	Jul 9, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/4291
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.