Method for optimizing memory access in a microprocessor including several logic cores upon resumption of executing an application, and computer implementing such a method
US10025633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2011 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Jul 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.