Patent · US Active

Memory type range register with write-back cache strategy for NVDIMM memory locations

US10025714B2 · kind B2 · utility

1Cited by

16References

8Claims

0Family size

Assignee

Super Micro Computer, Inc. · US

Inventors

Donald Han · San Jose, US
John Chen · San Francisco, US
Jason Chang · Fengxian, CN

Key dates

Filing date	Sep 30, 2016
Grant date	Jul 17, 2018
Priority date	—
Expiry date	Dec 14, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/205
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer system includes a dual in-line memory module (DIMM), such as a registered DIMM (RDIMM), and a non-volatile DIMM (NVDIMM). A central processing unit (CPU) of the computer system has internal cache memory locations for caching data for the DIMM and NVDIMM. A memory type range register (MTTR) of the CPU is set for write-back cache strategy for a range of memory locations in the DIMM and NVDIMM. The computer system includes a power supply that, in the event of a power failure, triggers a hardware non-maskable interrupt (NMI) and sustains power to the CPU to allow cached data to be saved to non-volatile memory locations in the NVDIMM before the computer system completely powers down.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.