Method in a memory management unit for managing address translations in two stages
US10025726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2014 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Aug 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.