Address translation stimuli generation for post-silicon functional validation
US10026500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Feb 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating address translation stimuli for post-silicon functional validation is provided. The method includes determining a plurality of memory configurations based on a plurality of translation tables used by a stimuli generator to solve a plurality of test templates, providing a test template from the plurality of test templates, selecting a memory configuration from the plurality of memory configurations based on the test template, a memory variable, and a set of testing parameters, identifying a translation table from the plurality of translation tables based on the test template, allocating a memory space for the translation table, and executing the test template on the stimuli generator based on the translation table, the memory space, and the set of testing parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.