Semiconductor memory devices having separation structures
US10026749B2 · kind B2 · utility
6Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2016 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Nov 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend in the first direction on the first cell array region and are spaced apart from each other in a second direction crossing the first direction, an insulation layer that covers the stack structures, and at least one separation structure that extends in the second direction on the peripheral region and penetrates the insulation layer in a direction normal to a top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.