Semiconductor device
US10026809B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2017 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Jul 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance. A gate spacer is disposed on sidewalls of a gate electrode running across the active patterns. Source/drain regions include a first to a third source/drain regions disposed on a region of one of the active patterns. The region of one of the active patterns is disposed adjacent to a side of the gate electrode. First and second protective insulation patterns are disposed on the substrate between the first and second active patterns below the first and second source/drain regions and between the second and third active patterns below the second and third source/drain regions, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.